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17:55
Apr 15
Apr 15
ISSCC 2026: NVIDIA & Broadcom CPO, HBM4 & LPDDR6, TSMC Active LSI, Logic-Based SRAM, UCIe-S and More
SSNLF
WDC
MRVL
TSM
INTC
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Samsung's HBM4 performance is closing the gap with SK Hynix, threatening the current HBM monopoly narrative.
The market prices SK Hynix as the undisputed king of HBM. However, Samsung's aggressive move to use a premium SF4 logic base die for HBM4 is yielding superior pin speeds (13 Gb/s) that exceed JEDEC standards. If Samsung secures major Nvidia Rubin allocations, expect a massive valuation catch-up trade as SK Hynix's premium compresses.
"The technical details presented at ISSCC... clearly demonstrate that Samsung’s HBM4 is competitive with its peers... and could challenge SK Hynix’s dominance in HBM."
SSNLF LONG
WDC/Kioxia's BiCS10 NAND achieves industry-leading bit density, setting up a structural margin advantage.
WDC's joint venture with Kioxia has quietly taken the density crown in NAND, beating SK Hynix by 30% in QLC configurations. This structural cost-per-bit advantage is not fully priced into WDC shares, positioning them to capture outsized margins and market share in the upcoming enterprise SSD upgrade cycle.
"SanDisk and Kioxia demonstrated their BiCS10 NAND... This is the highest reported NAND bit density, at 37.6 Gb/mm², dethroning the previous champion, SK Hynix’s 321L V9."
WDC LONG
Marvell's "Coherent-lite" optics perfectly address the emerging bottleneck of campus-scale AI clusters.
As AI training clusters grow too large for single buildings, datacenter campus interconnects (10-40km) become the new critical bottleneck. Marvell's Coherent-lite cuts power by 50% vs traditional coherent optics while eliminating heavy DSP latency, giving them a dominant, high-margin product for the upcoming wave of multi-building AI cluster buildouts.
"Marvell’s Coherent-lite transceiver targets a middle ground with respect to power consumption, cost and range, which is perfect for large datacenter campuses..."
MRVL LONG
TSMC's Active LSI (aLSI) packaging creates a new, high-margin moat that locks in AI accelerator customers.
The market views TSMC's CoWoS primarily as a capacity bottleneck, but misses the technological lock-in of their next-gen Active LSI packaging. By embedding active transistors into the bridge die, TSMC allows Nvidia and AMD to shrink their PHY area and pack more compute. This deepens TSMC's moat, ensuring pricing power remains absolute even as front-end node scaling slows.
"As designers eke out every bit of die space for next-generation AI accelerators, the switch to aLSI is inevitable."
TSM LONG
Intel's advanced packaging and interconnect IP are showing surprising technical leadership, offering a mispriced call option.
Market sentiment on Intel is abysmal, yet their 22nm UCIe-S interconnect beat a competitor's 3nm design, and their 18A hybrid bonding (M3DProc) showed massive 875 GB/s 3D bandwidth. This signals that Intel's advanced packaging IP remains world-class; if 18A yields even adequately, the custom silicon/foundry business is severely underpriced at current levels.
"Despite the node disadvantage, Intel has managed to best Cadence’s interconnect in data rate, channel length and shoreline bandwidth..."
INTC LONG
04:25
Apr 02
Apr 02
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