Ivan Chiam
· SemiAnalysis
· March 12, 2026 at 15:20
· ⏱ 16 min read
| Read on Substack ↗
Summary
The AI silicon shortage has shifted from packaging and power to TSMC's N3 logic wafer capacity and HBM memory, creating a structural bottleneck that will persist through at least 2027. This means TSMC has extreme pricing power over customers, while smartphone weakness may free up limited N3 capacity for AI accelerators but not enough to materially ease the crunch. The tightest constraint is memory, where HBM's disproportionate wafer consumption and Micron's lagging yields will keep supply tight.
•Anthropic added $6B of ARR in a single month (Feb 2026) driven by agentic coding platform Claude Code, and would have added more with more compute.
•Google's 2026 capex expectations have roughly doubled versus prior expectations, primarily from datacenter and server spend.
•TSMC's N3 effective utilization is expected to exceed 100% in the second half of 2026 as demand outpaces cleanroom expansion.
•AI-related N3 demand (accelerator, host CPU, networking) will take ~60% of N3 output in 2026 and surge to ~86% in 2027, nearly squeezing out smartphone and CPU wafers.
•HBM consumes roughly three times more wafer capacity per bit than commodity DRAM, a ratio that widens to nearly 4x with HBM4 and HBM4E.
•Micron is lagging behind SK Hynix and Samsung in meeting HBM4 pin speed requirements (~11 Gb/s), constraining effective HBM supply.
•Reallocating 25% of smartphone N3 wafer starts in 2026 could produce ~0.7M additional Rubin GPUs or ~1.5M additional TPU v7s, but memory and packaging would then become the next bottlenecks.
•Rising DDR DRAM prices have pushed DDR margins close to or above contracted HBM margins, reducing the incentive for memory suppliers to shift capacity toward HBM without higher pricing.
The article references 'Google and Broadcom’s TPU' as the first to adopt N3 with TPU v7, and notes huge volume increases for TPU in 2026 from both internal Google and external demand (Anthropic). Broa
The article references 'Google and Broadcom’s TPU' as the first to adopt N3 with TPU v7, and notes huge volume increases for TPU in 2026 from both internal Google and external demand (Anthropic). Broadcom’s custom ASIC business is directly tied to this N3 ramp.
Risk: Broadcom's TPU revenue is dependent on Google's spending pace; any slowdown in Google capex would impact AVGO. N3 capacity constraints could also limit TPU shipments.
The article explicitly names TSMC as 'kingmaker' among customers competing for limited N3 allocation, with effective utilization exceeding 100% and AI customers receiving priority due to higher ASPs.
The article explicitly names TSMC as 'kingmaker' among customers competing for limited N3 allocation, with effective utilization exceeding 100% and AI customers receiving priority due to higher ASPs. This pricing power and capacity leverage directly benefit TSMC's revenue and margins.
Risk: Any consumer demand collapse could reduce some wafer demand, but AI demand is multi-year committed; geopolitical risks around Taiwan remain.
The article states 'Micron is lagging behind in HBM4' as customers demand ~11 Gb/s pin speeds that remain difficult to achieve at acceptable yields. This competitive disadvantage relative to SK Hynix
The article states 'Micron is lagging behind in HBM4' as customers demand ~11 Gb/s pin speeds that remain difficult to achieve at acceptable yields. This competitive disadvantage relative to SK Hynix and Samsung could lead to market share loss in the highest-growth memory segment.
Risk: Micron could catch up if yields improve; consumer DRAM softness might offset some HBM weakness.
This newsletter, published March 12, 2026,
features Ivan Chiam
discussing AVGO, TSM, MU.
3 trade ideas extracted by AI with direction and confidence scoring.