ISSCC 2026: NVIDIA & Broadcom CPO, HBM4 & LPDDR6, TSMC Active LSI, Logic-Based SRAM, UCIe-S and More

Afzal Ahmad · SemiAnalysis · April 15, 2026 at 17:55 · ⏱ 56 min read  | Read on Substack ↗
Summary
The ISSCC 2026 roundup from SemiAnalysis presents detailed technical advancements across memory, optical interconnects, die-to-die interfaces, and processors, with direct implications for competitive positioning among leading semiconductor companies. Samsung's HBM4 shows strong pin-speed gains but trails in reliability and yield, SK Hynix leads in LPDDR6 density, TSMC's Active LSI promises tighter interconnects for AI accelerators, and Intel's UCIe-S offers a cost-effective die-to-die solution. These developments reinforce the ongoing race in AI hardware and advanced packaging, benefiting incumbents with the most integrated roadmaps.
  • Samsung HBM4 achieves 13 Gb/s per pin (2× JEDEC standard) using a logic base die (SF4) and 1c DRAM, but front-end yields are ~50% and margins lag SK Hynix.
  • Samsung LPDDR6 reaches 14.4 Gb/s at 1.025V; die density (0.360 Gb/mm²) is lower than LPDDR5X on 1b, attributed to dual-subchannel overhead.
  • SK Hynix LPDDR6 on 1c process reaches 14.4 Gb/s with estimated bit density of 0.59 Gb/mm², but shows worse power efficiency at low voltages vs Samsung.
  • SK Hynix GDDR7 on 1c achieves 48 Gb/s at 1.2V, with bit density 0.412 Gb/mm², significantly up from prior nodes.
  • TSMC Active LSI (aLSI) reduces PHY area by ~18% using Manhattan grid and embedded edge-triggered transceivers, demonstrated in a vehicle matching AMD’s MI450 with 0.36 pJ/b.
  • Intel’s UCIe-S on 22nm achieves 48 Gb/s/lane over 30mm organic substrate, outperforming Cadence’s N3E implementation in data rate and channel length.
  • Microsoft Maia 200 is a reticle-scale monolithic AI chip on N3P with 10+ PFLOPs FP4, 272 MB SRAM, and 28×400Gb/s D2D links, packaged on CoWoS-S.
  • MediaTek’s xBIT logic-based SRAM achieves 22-63% higher density and 30%+ lower power vs foundry 8T, using a 10-transistor balanced bitcell on N3E.
Read time 56 min
Length 56,724 chars
Category finance
Trade Ideas
Afzal Ahmad Analyst, SemiAnalysis
Broadcom demonstrated a 6.4T optical engine with 64 lanes of ~100G PAM4 in a Tomahawk 5 51.2T CPO system, using Fan-Out WLP. The paper shows egress transmitter performance meeting specs, reinforcing B
Broadcom demonstrated a 6.4T optical engine with 64 lanes of ~100G PAM4 in a Tomahawk 5 51.2T CPO system, using Fan-Out WLP. The paper shows egress transmitter performance meeting specs, reinforcing Broadcom's leadership in CPO for scale-out networking. While Broadcom will migrate to COUPE later, this generation proves their packaging and optical engine capability. Risk: Competition from Nvidia's COUPE and OCI MSA could shift standards; Broadcom's CPO margins may compress as volume ramps.
Afzal Ahmad Analyst, SemiAnalysis
Samsung's HBM4 demonstrated best-in-class pin speed (13 Gb/s) and aggressive adoption of SF4 logic base die, closing the gap with SK Hynix. However, lower 1c yields (~50%) and higher base die cost (SF
Samsung's HBM4 demonstrated best-in-class pin speed (13 Gb/s) and aggressive adoption of SF4 logic base die, closing the gap with SK Hynix. However, lower 1c yields (~50%) and higher base die cost (SF4 vs N12) pressure margins. The LPDDR6 PHY on SF2 also shows strong efficiency features. Overall, technological progress supports Samsung's HBM market share recovery, but reliability and margin headwinds remain. Risk: Yield improvement is uncertain; SK Hynix retains reliability advantage and could maintain HBM dominance.
Afzal Ahmad Analyst, SemiAnalysis
AMD's MI355X improvements detailed at ISSCC include doubling matrix throughput per CU on N3P, reducing IOD count from 4 to 2 (saving area/latency), and custom wire optimization cutting interconnect po
AMD's MI355X improvements detailed at ISSCC include doubling matrix throughput per CU on N3P, reducing IOD count from 4 to 2 (saving area/latency), and custom wire optimization cutting interconnect power ~20%. The TSMC Active LSI test vehicle matches AMD's MI450 design (2 base dies, 12 HBM4 stacks), suggesting early adoption of aLSI for next-gen AI GPUs. These architectural gains reinforce AMD's competitive positioning in AI accelerators. Risk: Software ecosystem and customer adoption remain key hurdles vs NVIDIA's CUDA; monolithic MI355X still trails NVIDIA's multi-die scaling in aggregate flops.
Afzal Ahmad Analyst, SemiAnalysis
Intel's UCIe-S die-to-die interface on 22nm achieved 48 Gb/s/lane over 30mm organic substrate, outperforming Cadence's N3E implementation in speed and reach. The presentation is likely a prototype for
Intel's UCIe-S die-to-die interface on 22nm achieved 48 Gb/s/lane over 30mm organic substrate, outperforming Cadence's N3E implementation in speed and reach. The presentation is likely a prototype for Diamond Rapids Xeon, enabling multi-die packaging without advanced interposers. If scaled to Intel 3, efficiency could improve significantly, strengthening Intel's server CPU competitive position. Risk: 22nm test chip efficiency is behind advanced nodes; adoption in Diamond Rapids requires die shrinks and validation at scale.
Afzal Ahmad Analyst, SemiAnalysis
SK Hynix unveiled first 1c LPDDR6 and GDDR7, with GDDR7 hitting 48 Gb/s and LPDDR6 density estimated at 0.59 Gb/mm², leading the DRAM density race. Their GDDR7 improvement from 0.309 to 0.412 Gb/mm² i
SK Hynix unveiled first 1c LPDDR6 and GDDR7, with GDDR7 hitting 48 Gb/s and LPDDR6 density estimated at 0.59 Gb/mm², leading the DRAM density race. Their GDDR7 improvement from 0.309 to 0.412 Gb/mm² indicates strong node progression. Despite trailing Samsung in low-voltage LPDDR6 efficiency, SK Hynix maintains overall DRAM technology leadership. Risk: Samsung's aggressive HBM4 performance could erode SK Hynix's HBM premium; GDDR7 demand may shift as NVIDIA de-emphasizes GDDR7 for Rubin CPX.
Afzal Ahmad Analyst, SemiAnalysis
Marvell presented an 800G coherent-lite transceiver targeting datacenter campus links up to 40km, using O-band for low dispersion and achieving 3.72 pJ/b (half of full coherent). This product fills a
Marvell presented an 800G coherent-lite transceiver targeting datacenter campus links up to 40km, using O-band for low dispersion and achieving 3.72 pJ/b (half of full coherent). This product fills a gap between direct-detect and long-haul coherent, expanding Marvell's optical portfolio for AI cluster interconnects. Risk: Coherent-lite is a niche application; adoption depends on hyperscaler campus buildouts and could be bypassed by DWDM solutions.
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