The EDA Primer: From RTL to Silicon

Gerald Wong · SemiAnalysis · May 12, 2026 at 02:32 · ⏱ 65 min read  | Read on Substack ↗
Summary
The article argues that semiconductor design faces a structural bottleneck: chip complexity grows 50% annually while design productivity improves only 20%, compounded by a shrinking engineer base and compressed timelines. This makes EDA software (Synopsys, Cadence, Siemens) the critical enabler for continued silicon scaling. For markets, the dominant EDA vendors and leading foundries (TSMC) are positioned as indispensable beneficiaries, while Intel's foundry competitiveness is questioned based on design tool limitations.
  • •Chip complexity grows ~50% per year driven by new nodes and larger SoCs, but design productivity improves only ~20% annually, creating an exponential gap in engineering effort required.
  • •Verification now consumes up to 70% of total project effort, and verification engineers are the fastest-growing job category in chip development, yet the industry cannot hire them fast enough.
  • •The three dominant EDA vendors are Synopsys (Design Compiler, Fusion Compiler, VCS), Cadence (Innovus, Genus, Xcelium), and Siemens EDA (Calibre, Questa).
  • •Foundry PDK access is tiered: anchor/JDA customers (Apple, AMD, Nvidia) get access 3+ years before production, while standard customers accept design rules as-is.
  • •Intel's 18A process initially had only 4 threshold voltage options vs TSMC's 6, making it harder to achieve the Pareto-optimal PPA curve, though Intel 18AP fixes this.
  • •Apple uses TSMC's 3-2 FinFlex for high-performance CPU cores and the denser 2-1 FinFlex for the rest of the die, demonstrating custom cell mixing for PPA optimization.
  • •The latest AMD MI455X packs 320 billion transistors across 12 logic dies on 2nm and 3nm processes with advanced 3D die stacking and HBM4.
  • •Open-source PDKs (e.g., SKY130) exist for education, but production designs rely on NDA-protected foundry PDKs with thousands of design rules.
Read time 65 min
Length 65,464 chars
Category finance
Trade Ideas
Gerald Wong Substack author, SemiAnalysis
The article repeatedly highlights Synopsys as the market leader in logic synthesis (Design Compiler), simulation (VCS), physical design (IC Compiler II, Fusion Compiler), signoff (IC Validator, PrimeT
The article repeatedly highlights Synopsys as the market leader in logic synthesis (Design Compiler), simulation (VCS), physical design (IC Compiler II, Fusion Compiler), signoff (IC Validator, PrimeTime), and TCAD (Sentaurus). As the design productivity gap widens, Synopsys tools become more essential, driving recurring license growth. Risk: Cyclical semiconductor capex slowdown could reduce EDA spending; competition from Cadence and open-source tools.
SNPS
Gerald Wong Substack author, SemiAnalysis
The article states that Intel's initial 18A had only 4 VT options vs TSMC's 6, making it harder to be on the Pareto optimal curve, and notes that Intel's Ponte Vecchio chip (47 dies, 5 nodes) faced ye
The article states that Intel's initial 18A had only 4 VT options vs TSMC's 6, making it harder to be on the Pareto optimal curve, and notes that Intel's Ponte Vecchio chip (47 dies, 5 nodes) faced years of delays with final performance 'nowhere near original targets.' This suggests Intel's foundry and design execution still lag TSMC. Risk: Intel could improve with 18AP and future nodes; the critique is based on historical data.
INTC
Gerald Wong Substack author, SemiAnalysis
Cadence is named as the other dominant EDA vendor with tools like Innovus (place-and-route), Genus (synthesis), Xcelium (simulation), Palladium (emulation), and Tempus (STA). The article notes that mo
Cadence is named as the other dominant EDA vendor with tools like Innovus (place-and-route), Genus (synthesis), Xcelium (simulation), Palladium (emulation), and Tempus (STA). The article notes that most large chip companies license at least two simulators (VCS and Xcelium), indicating Cadence's entrenched position. Risk: Same cyclical risk as SNPS; potential share loss to Synopsys' unified flow advantage.
CDNS
Gerald Wong Substack author, SemiAnalysis
TSMC is the foundry referenced throughout for advanced nodes (N2, N3, N5) and is the supplier for Apple, AMD, Nvidia, and others. The article highlights TSMC's FinFlex and NanoFlex technology as enabl
TSMC is the foundry referenced throughout for advanced nodes (N2, N3, N5) and is the supplier for Apple, AMD, Nvidia, and others. The article highlights TSMC's FinFlex and NanoFlex technology as enabling superior PPA through DTCO, and notes that anchor customers get early PDK access, reinforcing TSMC's competitive moat. Risk: Geopolitical risk from Taiwan; potential loss of leading-edge customers to Intel or Samsung.
TSM
More from SemiAnalysis
AI Value Capture - The Shift To Model Labs
May 01, 02:30
How Much Do GPU Clusters Really Cost?
Apr 20, 14:21
ISSCC 2026: NVIDIA & Broadcom CPO, HBM4 & LPDDR6, TSMC Active LSI, Logic-Based SRAM, UCIe-S and More
Apr 15, 17:55
The Great GPU Shortage – Rental Capacity – Launching our H100 1 Year Rental Price Index
Apr 02, 04:25
Dissecting Nvidia Blackwell - Tensor Cores, PTX Instructions, SASS, Floorsweep, Yield
Mar 31, 22:00

This newsletter, published May 12, 2026, features Gerald Wong discussing SNPS, INTC, CDNS, TSM. 4 trade ideas extracted by AI with direction and confidence scoring.

Speakers: Gerald Wong  · Tickers: SNPS, INTC, CDNS, TSM