EMIB-T Roadmap, Custom HBM, HBM4 Packaging Challenges, Microfluidic Cooling, Photonic Interconnects, and More

Afzal Ahmad · SemiAnalysis · July 02, 2026 at 17:25 · ⏱ 41 min read  | Read on Substack ↗
Summary
At ECTC 2026, Intel, Marvell, TSMC, and Microsoft disclosed advanced packaging technologies (EMIB-T, custom HBM, microfluidic cooling, optical interconnects) that are essential for overcoming limits in AI accelerator scaling. These developments signal a shift in competitive dynamics for the packaging ecosystem, with Intel narrowing the gap to TSMC's CoWoS and custom HBM enabling bandwidth/area gains for Marvell and Nvidia.
  • •Intel's EMIB-T reduces bump pitch to 36/35 µm and achieves 65% higher bump density than Granite Rapids, with 240×240 mm quarter-panel test vehicles demonstrated.
  • •Marvell's custom HBM reduces host ASIC area dedicated to HBM PHYs by ~60% and shortens interposer channel length from 6.5 mm to 1.5 mm using organic RDL.
  • •TSMC's micropillar direct-to-silicon cooling dissipates 5.3 kW at 8 LPM, outperforming lidless cold plates and enabling >5 kW uniform dissipation.
  • •Microsoft's microfluidic cooling on an Nvidia GH200 reduces junction-to-inlet thermal resistance by 51–60% for the GPU at 1 LPM, with minimal clogging over 6 months.
  • •Lightmatter's Passage M1000 uses a four-tile photonic interposer (~2100 mm²) with 15 ASIC chiplets, achieving >95% electrical assembly yield despite 59 µm warpage at reflow.
  • •Marvell's OMIB embeds photonic ICs in an organic RDL interposer only where needed, claiming bandwidth density of 1.8 Tbps/mm², and uses electro-absorption modulators for better thermal stability.
  • •Samsung proposed an 8-layer silicon interposer for HBM4E (20% fewer layers than estimated) with ultra-high-density capacitors, and showed hybrid copper bonding reduces stack thermal resistance by ~19% vs. TCB.
  • •Glass-core substrates from Corning/STATS ChipChipChipChipChipChipChipChip pass reliability with edge coating; Intel demonstrated a 510×515 mm 24-layer glass-core panel with embedded bridges and optical waveguides.
Read time 41 min
Length 41,619 chars
Category finance
Ideas
Afzal Ahmad Analyst, SemiAnalysis
Intel's EMIB-T roadmap shows validated 36/35 µm bump pitch, 240×240 mm packages, and simulated HBM4E performance up to 16 Gb/s, closing the gap to TSMC's CoWoS. The article states EMIB-T is 'the most
Intel's EMIB-T roadmap shows validated 36/35 µm bump pitch, 240×240 mm packages, and simulated HBM4E performance up to 16 Gb/s, closing the gap to TSMC's CoWoS. The article states EMIB-T is 'the most credible alternative to TSMC's CoWoS platform for large-package AI accelerators.' Risk: Intel still lags TSMC in volume execution and ecosystem maturity; warpage issues at large sizes may delay certification.
INTC
Afzal Ahmad Analyst, SemiAnalysis
Marvell's custom HBM reduces host die area by ~60% and shortens interposer routing, with a 4.1 TB/s example at 32 Gb/s. Its OMIB optical interconnect achieves 1.8 Tbps/mm². These advances position Mar
Marvell's custom HBM reduces host die area by ~60% and shortens interposer routing, with a 4.1 TB/s example at 32 Gb/s. Its OMIB optical interconnect achieves 1.8 Tbps/mm². These advances position Marvell as a key packaging innovator for AI accelerators. Risk: Custom HBM requires memory vendor collaboration (e.g., SK Hynix, Samsung) and may face adoption hurdles; OMIB is still in test vehicle phase.
MRVL
Afzal Ahmad Analyst, SemiAnalysis
The article notes that 'Nvidia announced that Feynman would use custom HBM' and estimates ~16% of Rubin GPU die area is HBM-related logic. Custom HBM offloads that burden to the base die, freeing area
The article notes that 'Nvidia announced that Feynman would use custom HBM' and estimates ~16% of Rubin GPU die area is HBM-related logic. Custom HBM offloads that burden to the base die, freeing area for compute. This directly benefits Nvidia's future GPU performance and cost. Risk: Custom HBM introduces supply chain complexity and potential vendor lock-in; execution risks in integration.
NVDA
Afzal Ahmad Analyst, SemiAnalysis
TSMC's micropillar cooling dissipated 5.3 kW on CoWoS-R, and its CoWoS platform remains the volume leader. The article notes TSMC's CoWoS-R/L 'remain limited by the circular wafer' but still dominate.
TSMC's micropillar cooling dissipated 5.3 kW on CoWoS-R, and its CoWoS platform remains the volume leader. The article notes TSMC's CoWoS-R/L 'remain limited by the circular wafer' but still dominate. TSMC's cooling and interposer innovations reinforce its packaging leadership. Risk: Intel's EMIB-T and panel-scale alternatives could erode TSMC's advantage over time; the article also notes TSMC presented only 3 papers vs. Intel's 12, suggesting a shift in innovation intensity.
TSM
More from SemiAnalysis
TokenBudgeting: Our Conversations with Enterprises on Token Spend
Jun 30, 18:32
US Grid Constraints: Towards 40GW+ of Behind-The-Meter Datacenter by 2028?
Jun 25, 19:48
China’s CXMT Is Set to Challenge DRAM Incumbents
Jun 23, 14:51
Stop Saying Half of 2026 US Datacenter Capacity Is Canceled
Jun 18, 15:54
RL Systems Mind the Gap: Matching Trainer and Generator Throughput
Jun 16, 17:32

This newsletter, published July 02, 2026, features Afzal Ahmad discussing INTC, MRVL, NVDA, TSM. 4 trade ideas extracted by AI with direction and confidence scoring.

Speakers: Afzal Ahmad  · Tickers: INTC, MRVL, NVDA, TSM