Ep. 019 - Inside the STEEL Lab: From Package to Transistor (Teardown Lab)

Summary

The STEEL teardown lab team explains how they analyze chips from package to transistor, using the SMIC N+3 process and Huawei Kirin 9030 SOC as a case study. They detail die shots, NPU discovery, cell height shrink, and standard cell libraries, while discussing how export bans forced SMIC to innovate without EUV. The conversation also covers future teardown challenges like backside power, gate-all-around, and advanced packaging.

• The STEEL lab provides competitive intelligence by tearing down chips to the transistor level.
• SMIC's N+3 node shrank the M0 layer over 15% and reduced SRAM area 10-20% without EUV.
• Huawei's Kirin 9030 features an upgraded NPU with two tiny cores, discovered through die shot annotation.
• Export restrictions forced SMIC to innovate, reaching parity with leading fabs but making process compromises.
• Cell height reduction from N+2 to N+3 improves transistor density; library choices affect performance and area.
• Nvidia's A100 used a 4-fin HPC library, showing how specialized libraries optimize high-current GPUs.
• Backside power, gate-all-around, and hybrid bonding create new teardown challenges and analytical opportunities.
• Huawei is using logic folding with sub-1.5-micron pitch hybrid bonds to circumvent DUV scaling limits.