Damnang
· Damnang’s Substack
· June 22, 2026 at 07:54
· ⏱ 9 min read
| Read on Substack ↗
Summary
SPHBM4 (JESD330-4) fundamentally alters HBM packaging by removing the expensive silicon interposer, allowing memory to attach directly to a cheap organic substrate. This shifts value and technical difficulty from the substrate to the base die, which now must incorporate high-speed SerDes and PHY logic. The change reshapes competition among memory makers (Samsung, SK hynix) and foundries (TSMC, NVIDIA), with packaging capacity remaining the true bottleneck for AI accelerator shipments.
•SPHBM4 reuses HBM4 DRAM stacks unchanged, replacing only the bottom base die to enable direct attachment to organic substrate.
•HBM4 used 2,048 data pins requiring a silicon interposer; SPHBM4 cuts pin count to 512 by employing 4:1 serialization, maintaining total bandwidth while allowing wider bump pitch compatible with organic substrates.
•The base die must now handle fourfold faster signaling (SerDes/PHY), increasing complexity, power, and heat — moving base die design closer to high-speed communication chips than simple memory components.
•Packaging accounts for only a single-digit to low-teens share of accelerator cost, but its capacity governs shipment volume, making it a critical bottleneck.
•The standard was published by JEDEC in June 2026; adoption timeline is not specified but will determine the pace of supply chain disruption.
•Memory companies now need logic design capability (high-speed PHY, SerDes) beyond traditional DRAM stacking skills — a new battleground for competitive positioning.
The article identifies packaging capacity as the key shipment bottleneck and notes that the shift from silicon interposer to advanced logic in the base die increases demand for high-speed manufacturin
The article identifies packaging capacity as the key shipment bottleneck and notes that the shift from silicon interposer to advanced logic in the base die increases demand for high-speed manufacturing and design. TSMC is the dominant provider of advanced logic fabrication and advanced packaging (e.g., CoWoS), positioning it to capture value from both the base die production and the broader packaging ecosystem.
Risk: If memory companies develop in-house base die capabilities or partner with other foundries, TSMC's market share could be challenged. Adoption rate of SPHBM4 is uncertain.