How the Memory Tax Gets Solved

Damnang · Damnang’s Substack · June 19, 2026 at 01:01 · ⏱ 10 min read  | Read on Substack ↗
Summary
The memory shortage is not a cyclical supply-demand issue but a structural bottleneck caused by HBM's disproportionate wafer consumption (3x vs DDR5) and memory makers' deliberate capacity discipline, keeping DRAM tight through at least 2027. The article argues that the solution lies in nine 'detour' technologies—ranging from using NAND as memory to optical interconnects and software tiering—which collectively aim to reduce reliance on expensive DRAM. For markets, this means persistent pricing power for memory makers and growing value in companies enabling memory substitution and system-level efficiency.
  • •HBM consumes 3x the wafer capacity of DDR5 per part; by 2027 HBM will take 30% of wafer starts despite only 13% of bit supply.
  • •First-quarter DRAM contract prices jumped 90-95% QoQ, with DDR4 pricing higher than DDR5—a sign of structural supply pullback.
  • •New DRAM fabs from Micron, SK hynix, and Samsung do not ship until 2027-2028, and existing capacity is allocated to HBM first.
  • •NAND flash is 10-50x cheaper per bit than DRAM, and its capacity can grow via vertical stacking (no EUV constraint), making it the key substitution medium.
  • •AMD acquired Israeli startup MEXT, which builds a prediction layer to make flash behave like DRAM—illustrating the software-driven approach to circumvent the memory tax.
  • •The article identifies nine engineering tracks to solve the memory tax, dividing them into changing the medium, cutting data movement, and system/software-level optimizations.
Read time 10 min
Length 10,766 chars
Category finance
Ideas
Damnang Substack author, Damnang’s Substack
Article includes a section 'Front 2: Nvidia seizes the entire memory hierarchy as interface', implying Nvidia is positioning to control memory standards across the stack, which would strengthen its ec
Article includes a section 'Front 2: Nvidia seizes the entire memory hierarchy as interface', implying Nvidia is positioning to control memory standards across the stack, which would strengthen its ecosystem lock-in. The article also discusses HBM tightness, which pressures Nvidia's GPU supply chain but also reinforces its need for innovative memory solutions. Risk: If Nvidia's memory interface control faces pushback from hyperscalers or memory makers, its margin advantage could erode.
NVDA
Damnang Substack author, Damnang’s Substack
The article uses AMD's acquisition of MEXT as a clean example of how companies are detouring around the memory bottleneck. MEXT's prediction layer lets flash mimic DRAM behavior, reducing reliance on
The article uses AMD's acquisition of MEXT as a clean example of how companies are detouring around the memory bottleneck. MEXT's prediction layer lets flash mimic DRAM behavior, reducing reliance on scarce DRAM. This suggests AMD is proactively investing in memory-agnostic compute, potentially improving its competitive position against Nvidia in AI inference. Risk: Integration risk and uncertain performance of software-based flash-as-DRAM solutions vs. hardware approaches (HBM, CXL).
AMD
Damnang Substack author, Damnang’s Substack
Article repeatedly cites EUV scaling as the bottleneck for adding DRAM capacity ('requires EUV scaling', 'EUV constraint'). ASML is the sole supplier of EUV lithography systems. Any expansion or upgra
Article repeatedly cites EUV scaling as the bottleneck for adding DRAM capacity ('requires EUV scaling', 'EUV constraint'). ASML is the sole supplier of EUV lithography systems. Any expansion or upgrade of DRAM fabs (Micron's Idaho, SK hynix's Yongin, Samsung's Taylor) will require ASML tools, making it a structural beneficiary of memory investment. Risk: Export controls or geopolitical restrictions could limit ASML's sales to certain memory makers, dampening near-term demand.
ASML
Damnang Substack author, Damnang’s Substack
Article quantifies Micron's HBM-to-DDR5 wafer consumption ratio (3:1) and cites TrendForce data showing DRAM contract prices rising 90-95% QoQ, then 58-63% next quarter. As a major DRAM maker, Micron
Article quantifies Micron's HBM-to-DDR5 wafer consumption ratio (3:1) and cites TrendForce data showing DRAM contract prices rising 90-95% QoQ, then 58-63% next quarter. As a major DRAM maker, Micron directly benefits from structural shortage and pricing power through at least 2027. Risk: If AI demand slows or NAND substitution accelerates faster than expected, DRAM prices could normalize earlier than consensus.
MU
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This newsletter, published June 19, 2026, features Damnang discussing NVDA, AMD, ASML, MU. 4 trade ideas extracted by AI with direction and confidence scoring.

Speakers: Damnang  · Tickers: NVDA, AMD, ASML, MU