Is SMIC N+3’s Metal Pitch Smaller than Intel 18A’s?

STEEL Team · SemiAnalysis · June 14, 2026 at 19:14 · ⏱ 48 min read | Read on Substack ↗

Summary

SMIC's N+3 process achieves TSMC N6-class logic density (32.5 nm M0 pitch) through aggressive DUV multi-patterning and DTCO, but at the cost of complexity, efficiency, and maturity. Huawei's Kirin 9030 on N+3 shows incremental CPU/GPU gains but still lags years behind TSMC/Apple nodes; export controls have forced China toward 3D stacking (LogicFolding) to compensate. This validates the enduring advantage of EUV lithography and leading-edge foundries, making TSMC and ASML key beneficiaries of the scaling gap.

•SMIC N+3 has a 32.5 nm minimum metal pitch (M0) vs Intel 18A's 36 nm in Panther Lake, but the article calls this a 'cherry-picked metric' since Intel's full interconnect stack and backside power are superior.
•N+3 reaches a transistor density of 113.4 MTr/mm² vs TSMC N6's 107.7 MTr/mm², achieved without EUV via SAQP and DTCO techniques like COAG and SDB.
•The Kirin 9030's TaiShan prime core is roughly Cortex-X2 class per clock (2021 design), trailing Apple M5 P-core by 2.7× in absolute integer performance at similar power.
•Huawei's Maleoon 935 GPU is 70% faster than the prior generation but still ~2.4× slower than the Snapdragon 8 Elite Gen 5 in 3DMark Wild Life Extreme.
•SRAM bitcell scaling on N+3 improved ~19% from N+2, with a theoretical 6T HDC density of 38.5 Mib/mm² (roughly on par with TSMC N7/N6).
•Huawei's 'LogicFolding' roadmap aims to reach foundry 14A-equivalent density by 2031 via 3D stacking, but densities are measured per package footprint, not per planar die.
•The article highlights that export controls forced SMIC to use DUV quadruple patterning for M0 (32.5 nm pitch), increasing mask count and overlay sensitivity, while TSMC N6 uses simpler double patterning at ~40 nm.
•SMIC is licensing N+2/N+3 processes to HLMC/Hua Hong, and Chinese EDA tools are being developed for LogicFolding, diffusing manufacturing knowledge beyond SMIC.

Read time 48 min

Length 48,153 chars

Category finance

Ideas

STEEL Team Substack author, SemiAnalysis

The article repeatedly shows TSMC's EUV-based N6 node achieving competitive density with far lower complexity and process risk than SMIC N+3. TSMC's N3/N2 nodes (used by Apple/Qualcomm) deliver 2-3x b

The article repeatedly shows TSMC's EUV-based N6 node achieving competitive density with far lower complexity and process risk than SMIC N+3. TSMC's N3/N2 nodes (used by Apple/Qualcomm) deliver 2-3x better performance and efficiency, reinforcing TSMC's structural advantage. Risk: Geopolitical restrictions on equipment sales to China could escalate, but TSMC's leading-edge capacity remains the primary beneficiary of the gap.

STEEL Team Substack author, SemiAnalysis

SMIC's reliance on DUV SAQP for 32.5 nm M0 and inability to use EUV directly validates ASML's monopoly on high-NA EUV tools needed for sub-30 nm metal pitches at leading nodes. The article describes S

SMIC's reliance on DUV SAQP for 32.5 nm M0 and inability to use EUV directly validates ASML's monopoly on high-NA EUV tools needed for sub-30 nm metal pitches at leading nodes. The article describes SMIC's multi-patterning complexity as an expensive workaround. Risk: Export controls could limit ASML's China revenue, but the broader demand from TSMC/Intel/Samsung remains robust.

STEEL Team Substack author, SemiAnalysis

Although Intel 18A's M0 pitch (36 nm) is wider than SMIC N+3 (32.5 nm), the article clarifies that this is a cherry-picked metric and Intel's full stack (PowerVia, 1:1 M1-to-gate ratio, backside power

Although Intel 18A's M0 pitch (36 nm) is wider than SMIC N+3 (32.5 nm), the article clarifies that this is a cherry-picked metric and Intel's full stack (PowerVia, 1:1 M1-to-gate ratio, backside power) is superior. Intel's HD library density on 18A is still ~38% higher than SMIC N+3 in Bohr density. Risk: Intel's 18A ramp and customer adoption remain uncertain, and the article notes Panther Lake currently ships with the looser 36 nm pitch, not the 32 nm design target.

STEEL Team Substack author, SemiAnalysis

The article uses AMD's MI450X (N2 top die on N3P base die) as an example of how 3D stacking yields 460.2 MTr/mm² per package footprint, far ahead of Huawei's 2031 target. This underscores AMD's advant

The article uses AMD's MI450X (N2 top die on N3P base die) as an example of how 3D stacking yields 460.2 MTr/mm² per package footprint, far ahead of Huawei's 2031 target. This underscores AMD's advantage in advanced packaging and multi-die integration. Risk: AMD's data center GPU market share faces intense competition from NVIDIA and custom ASICs.

STEEL Team Substack author, SemiAnalysis

The article benchmarks Apple M5 P-core as 2.7× faster in absolute integer performance at similar power vs Huawei's prime core, and Apple's efficiency cores deliver 20% higher performance at 1 W vs 4.5

The article benchmarks Apple M5 P-core as 2.7× faster in absolute integer performance at similar power vs Huawei's prime core, and Apple's efficiency cores deliver 20% higher performance at 1 W vs 4.5 W. This validates Apple's lead in both process (N3P) and microarchitecture. Risk: Apple's growth is tied to consumer demand; no direct China exposure in this context.

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