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The Memory Crisis: Can CXL Be the Answer?

Damnang · Damnang’s Substack · July 06, 2026 at 02:55 · ⏱ 17 min read  | Read on Substack ↗
Summary
CXL (Compute Express Link) is experiencing a revival driven by the shift from AI training to inference, a severe memory capacity crisis pushing hyperscaler memory spend from 8% to 30% of capex, and PCIe 6.0 bandwidth now matching memory-channel speeds. This creates a new memory tier between DRAM and SSD, expanding total DRAM demand without cannibalizing HBM, but the article provides no explicit trade recommendations or disclosed positions.
  • Hyperscaler memory spend rose from ~8% of total capex in 2023–2024 to ~30% in 2026, a nearly fourfold jump driven by AI demand.
  • CXL was declared 'dead in the AI era' in early 2024 because training workloads prioritized GPU-to-GPU bandwidth over memory capacity.
  • Three factors revived CXL: inference workloads require large KV caches (80–120GB per GPU) that fit poorly in expensive HBM; memory crisis makes pooling and reusing old DRAM economical (Meta's Vistara paper); PCIe 6.0 x16 delivers ~128GB/s, matching 2.5 DDR5 memory channels.
  • CXL memory adds a tier between local DRAM (latency ~100ns) and SSDs (latency ~100μs), with application-level latency penalty of only 5–10μs at 95–100% throughput in Montage Technology demos.
  • Deployment evolves in three stages: direct attach (current volume), pooling (shared 100TiB+ pools), and fabric (rack-scale shared memory from CXL 3.1 onward).
  • Microsoft previewed CXL-attached memory in Azure M-series VMs in Nov 2025; Meta deployed CXL with revived DDR4 at hyperscale production; CXL 4.0 spec arrived Nov 2025 with PCIe 7.0 base at 128GT/s.
Read time 17 min
Length 17,887 chars
Category finance
Ideas
Damnang Substack author, Damnang’s Substack
The article states DRAM prices are 'soaring' and hyperscalers cannot secure enough volume, and CXL modules use 'ordinary DRAM' — so every CXL-attached server adds DRAM content. Micron is a major DRAM
The article states DRAM prices are 'soaring' and hyperscalers cannot secure enough volume, and CXL modules use 'ordinary DRAM' — so every CXL-attached server adds DRAM content. Micron is a major DRAM supplier and benefits from the structural increase in total DRAM demand per server, even as CXL creates a new tier rather than replacing HBM. Risk: CXL adoption may ramp slower than expected if PCIe 7.0 integration faces delays or if hyperscalers prioritize HBM3E capacity expansion over CXL.
Damnang Substack author, Damnang’s Substack
The article outlines a CXL ecosystem layer including 'switches' for memory pooling, and Broadcom is the dominant supplier of PCIe switches and retimers. The shift to PCIe 6.0/7.0 and CXL 3.1/4.0 neces
The article outlines a CXL ecosystem layer including 'switches' for memory pooling, and Broadcom is the dominant supplier of PCIe switches and retimers. The shift to PCIe 6.0/7.0 and CXL 3.1/4.0 necessitates advanced switch silicon, and Broadcom's Tomahawk and Jericho families are direct beneficiaries of data center memory disaggregation. Risk: Competition from Marvell or custom hyperscaler switch ASICs could pressure Broadcom's CXL switch market share.
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