Идеи
The article argues that OpenAI's custom chip beats Blackwell on perf/W and that 'The CUDA moat is potentially dead given how fast OpenAI can bring up new models on their silicon.'
The article argues that OpenAI's custom chip beats Blackwell on perf/W and that 'The CUDA moat is potentially dead given how fast OpenAI can bring up new models on their silicon.'
Risk: Nvidia's software ecosystem remains deeply entrenched outside of frontier labs, and their merchant silicon is still the default for the broader market.
Broadcom is explicitly named as OpenAI's ASIC design partner for Jalapeño and the provider of the 102.4T Tomahawk 6 switches used in the Chana switch trays for the scale-up network.
Broadcom is explicitly named as OpenAI's ASIC design partner for Jalapeño and the provider of the 102.4T Tomahawk 6 switches used in the Chana switch trays for the scale-up network.
Risk: Custom ASIC margins are typically lower than merchant silicon margins, and volume depends entirely on OpenAI's deployment success.
TSMC is manufacturing the Jalapeño compute die on its N3P node, the I/O chiplet on N3E, and handling the CoWoS packaging for the high-volume ramp.
TSMC is manufacturing the Jalapeño compute die on its N3P node, the I/O chiplet on N3E, and handling the CoWoS packaging for the high-volume ramp.
Risk: Capacity constraints on advanced nodes and CoWoS packaging could limit the volume of OpenAI's rollout.
The article explicitly notes that 'The system level design is done in partnership with Celestica,' giving them direct exposure to OpenAI's rack-scale hardware rollout.
The article explicitly notes that 'The system level design is done in partnership with Celestica,' giving them direct exposure to OpenAI's rack-scale hardware rollout.
Risk: Hardware manufacturing and system integration is a low-margin business subject to intense competition.
AMD is supplying the host CPUs for the system, with the article noting each host rack houses '16 host CPU trays... each houses two Turin-class AMD EPYC CPUs.'
AMD is supplying the host CPUs for the system, with the article noting each host rack houses '16 host CPU trays... each houses two Turin-class AMD EPYC CPUs.'
Risk: Host CPU revenue is a relatively small portion of total AI cluster spend compared to the accelerators and networking.
This newsletter, published August 25, 2026,
features Bryan Shan
discussing NVDA, AVGO, TSM, CLS, AMD.
5 trade ideas extracted by AI with direction and confidence scoring.
Speakers:
Bryan Shan
· Tickers:
NVDA,
AVGO,
TSM,
CLS,
AMD