Chip design from the bottom up – Reiner Pope

Summary

Reiner Pope gives a bottom-up blackboard lecture on how AI chips work, from logic gates and multiply-accumulate circuits to systolic arrays, Tensor Cores, FPGAs, ASICs, GPUs, and TPUs. The discussion focuses on compute versus communication, clocking, low-precision arithmetic, and architectural trade-offs. The main market-facing implication is Nvidia's B300-and-beyond shift to larger FP4 speedups as low-precision compute becomes more important.

• Chip primitives are built from simple logic gates, with matrix multiplication relying on multiply-accumulate operations.
• Systolic arrays and Tensor Cores were introduced to reduce register-file data movement and improve compute density.
• Low-precision arithmetic benefits from quadratic area scaling, and Nvidia's B300+ specs show FP4 at 3x FP8 throughput.
• FPGAs offer deterministic latency and flexibility but are less efficient than ASICs at volume.
• CPUs, GPUs, and TPUs differ in parallelism, caches, branch prediction, and systolic array organization.
• MatX is publicly working on a splittable systolic array to combine large and small systolic array benefits.
• The episode is primarily educational rather than an explicit stock-picking or asset-allocation discussion.