Cadence reported a strong Q2 2026 with record backlog and raised full-year guidance to 19% revenue growth. The call focused on agentic AI as a TAM expansion driver, with multiple AI super agents gaining traction. Management highlighted deepening partnerships with Intel, Samsung, and TSMC, and noted broad-based strength across all product groups, especially IP (40%+ growth) and hardware (supply-constrained). Raised FY2026 revenue guidance to $6.26-6.34B (19% growth), non-GAAP EPS $8.05-8.15, operating margin 43.75-44.75%.
Cadence reported a strong Q2 2026 with record backlog and raised full-year guidance to 19% revenue growth. The call focused on agentic AI as a TAM expansion driver, with multiple AI super agents gaining traction. Management highlighted deepening partnerships with Intel, Samsung, and TSMC, and noted broad-based strength across all product groups, especially IP (40%+ growth) and hardware (supply-constrained). Raised FY2026 revenue guidance to $6.26-6.34B (19% growth), non-GAAP EPS $8.05-8.15, operating margin 43.75-44.75%.
Management's tone was highly confident, driven by record backlog, broad-based growth across all product groups, and the largest single-quarter revenue raise in company history; they emphasized that competitive position has never been better.
Guidance · revenue to $6.3B
Agentic AI is a demand accelerator for Cadence as autonomous agents expand the design exploration space and call underlying physically accurate engines more often, creating a durable tailwind for long-term TAM expansion. Early customer results show 2x to 40x productivity…
Record backlog of $8.1 billion. Management's tone was highly confident, driven by record backlog, broad-based growth across all product groups, and the largest single-quarter revenue raise in company history; they emphasized that competitive position has never been better.
Agentic AI is a demand accelerator for Cadence as autonomous agents expand the design exploration space and call underlying physically accurate engines more often, creating a durable tailwind for long-term TAM expansion. Early customer results show 2x to 40x productivity improvements, but management is not assuming a sudden step function in guidance yet.
Record backlog of $8.1 billion. Management's tone was highly confident, driven by record backlog, broad-based growth across all product groups, and the largest single-quarter revenue raise in company history; they emphasized that competitive position has never been better.
Hardware remains supply constrained by customer demand rather than demand constrained, and the company is building systems as quickly as possible to deliver against backlog. Management also noted deliberate investments in strategic opportunities like Intel and Hexagon integration, driving slightly lower second-half margins.
Management's tone was highly confident, driven by record backlog, broad-based growth across all product groups, and the largest single-quarter revenue raise in company history; they emphasized that competitive position has never been better.
“I mean, you know, if there is one bottleneck, you know, the customers come up with different memory architectures to solve that bottleneck or different networking architecture.”
“We secured our first-ever Tensilica DSP design win with ST Microelectronics, reinforcing our strength in automotive and audio applications.”
“hardware still remains supply constrained by customer demand rather than demand constrained. And we're building the systems as quickly as we can to deliver against the backlog.”
| Metric | Period | Range | Midpoint | Status |
|---|---|---|---|---|
| EPS | FY2026 | $8.05–$8.15 | $8.10 | RAISED |
| Op margin | FY2026 | 43.75%–44.75% | 44.25% | RAISED |
| Revenue | FY2026 | $6.26B–$6.34B | $6.3B | RAISED |
| Revenue | FY2026 Q3 | $1.595B–$1.625B | $1.61B | GUIDED |
| Issued | Metric | Target | Guide | Actual | Outcome |
|---|---|---|---|---|---|
| FY2026 Q1 | EPS | FY2026 Q2 | $2.02–$2.08 | $2.11 | Met / beat |
| FY2026 Q1 | Op margin | FY2026 Q2 | 44.5%–45.5% | 28.42% | Missed |
| FY2026 Q1 | Revenue | FY2026 Q2 | $1.555B–$1.595B | $1.5845B | Met / beat |
| FY2025 Q4 | Revenue | FY2026 Q1 | $1.42B–$1.46B | $1.4742B | Met / beat |
Cadence secured its first Tensilica DSP design win with STMicroelectronics, signaling STM's increasing investment in automotive/audio DSP capabilities. — Adoption of Cadence's DSP IP suggests STM is expanding its product roadmap in automotive and audio, areas with high growth potential.
… quarter growing over 40% year-over-year. AI performance is increasingly constrained by data movement, memory bandwidth, and advanced packaging. And our differentiated IP portfolio continued to see strong adoption. This was reflected in the strong demand for our star IP portfolio in AI and HPC applications, including PCIe, UCIe, HBM, and LP DDR6. We also expanded engagement with leading memory, semiconductor and aerospace customers. We secured our first-ever Tensilica DSP design win with ST Microelectronics, reinforcing our strength in automotive and audio applications. Core EDA grew 18% year-over-year, driven by growing adoption of our AI solutions. Proliferation of our digital full-flow solutions continued, and we saw expanded adoption of Tempus and Certus sign-off tools on leading edge designs, with wins across hyperscalers, top semiconductor companies, and startups. We also expanded our implementation and sign-off footprint at frontier AI companies as well as at a marquee ASIC silicon vendor, underscoring their differentiated value in enabling the industry's most advanced design. In analog, we had a significant competitive win with Spectre at a leading semiconductor …
Cadence's hardware business (Palladium/Protium) remains supply-constrained by customer demand; systems are built as quickly as possible to meet backlog. — Persistent hardware tightness indicates that leading chip designers (including hyperscalers and semiconductor firms) are aggressively investing in verification capacity, a leading indicator of design activity.
“At Computex 2026, together with Nvidia, we introduced the industry's first fully autonomous virtual AI design engineer”
… flow from digital analog design and verification to advance packaging and PCB. We see strong early traction across our AI superagent portfolio with initial customer results demonstrating meaningful productivity improvement and better design outcomes. A chip stack AI superagent enabling higher verification productivity and faster design cycles has more than 20 customer engagements and is already deployed in production across multiple chip designs. At Computex 2026, together with Nvidia, we introduced the industry's first fully autonomous virtual AI design engineer, extending chip stack to even higher levels of autonomy. Early customer results include more than 40X faster RTL validation, reducing a typical five-week verification cycle to less than a day on a state-of-the-art advanced node design. In analog and custom design, Virastack is seeing strong customer interest with more than 25 customer engagement, achieving 2x to 10x productivity improvements compared to traditional design flows. InnoStack is also building momentum as customers adopt agentic AI for Advanced Node SoC Design. During the quarter, Rapid has announced a collaboration to integrate the Cadence InnoStack AI …
Cadence is deepening its partnership with Samsung on advanced nodes, likely expanding its IP and EDA footprint in Samsung's foundry ecosystem.
“We also deepen our collaboration with Samsung Foundry, on two-nanometer and 3D IC technologies, combining our AI-driven flows and design IP”
… to a 2x faster design turnaround. We continue to deepen our strategic partnerships across the ecosystem. We expanded our collaboration with Intel through a multi-year engagement focused on enabling its 14-year process, leveraging our design IP and agentic AI-based EDA to co-optimize tool flows and methodologies for next-generation HPC and mobile design. This agreement is expected to be a meaningful driver of growth over the next few years. We also deepen our collaboration with Samsung Foundry, on two-nanometer and 3D IC technologies, combining our AI-driven flows and design IP to enable next-generation AI, HPC, and mobile systems. Now turning to our businesses, we are pleased that all product groups delivered double-digit year-over-year growth. Our IP business had an outstanding quarter growing over 40% year-over-year. AI performance is increasingly constrained by data movement, memory bandwidth, and advanced packaging. And our differentiated IP portfolio continued to see strong adoption. This was reflected in the strong demand for our star IP portfolio in AI and HPC applications, including PCIe, UCIe, HBM, and LP DDR6. We also expanded engagement with leading memory, …
Continued collaboration with TSMC on advanced packaging for AI workloads underscores TSMC's critical role in Cadence's multi-die design ecosystem.
“With our 3D IC technology and collaboration with TSMC's 3D Fabric Advanced Packaging Solutions, we are enabling customers to confidently design cutting-edge silicon”
… added 12 new logos and saw meaningful expansion with several marquee AI customers, as well as a notable competitive win with a major AI infrastructure provider. System design and analysis revenue grew 37% year over year. As AI system complexity increases, customers are increasingly turning to our advanced packaging and PCB solutions. Allegro XAI was adopted by several customers driven by significant layout design time reduction. With our 3D IC technology and collaboration with TSMC's 3D Fabric Advanced Packaging Solutions, we are enabling customers to confidently design cutting-edge silicon for increasingly demanding AI workloads. In structural simulation, our beta CAE business had several competitive displacements. While the integration of recently acquired Hexagon's DNE business is progressing well with key deals closed with top customers. There is strong customer interest in our integrated full flow that combines our multi-physics products across the electrical, PFD, and structural domains to best address next generation system design needs, including in the emerging field of physical AI. In summary, Q2 was a great quarter for Cadence, and I'm delighted with the continued …
Cadence's hardware business (Palladium/Protium) remains supply-constrained by customer demand; systems are built as quickly as possible to meet backlog. — Persistent hardware tightness indicates that leading chip designers (including hyperscalers and semiconductor firms) are aggressively investing in verification capacity, a leading indicator of design activity.
“We expanded our collaboration with Intel through a multi-year engagement focused on enabling its 14-year process, leveraging our design IP and agentic AI-based EDA”
… 2x to 10x productivity improvements compared to traditional design flows. InnoStack is also building momentum as customers adopt agentic AI for Advanced Node SoC Design. During the quarter, Rapid has announced a collaboration to integrate the Cadence InnoStack AI superagent into its AI agent design solution, targeting up to a 2x faster design turnaround. We continue to deepen our strategic partnerships across the ecosystem. We expanded our collaboration with Intel through a multi-year engagement focused on enabling its 14-year process, leveraging our design IP and agentic AI-based EDA to co-optimize tool flows and methodologies for next-generation HPC and mobile design. This agreement is expected to be a meaningful driver of growth over the next few years. We also deepen our collaboration with Samsung Foundry, on two-nanometer and 3D IC technologies, combining our AI-driven flows and design IP to enable next-generation AI, HPC, and mobile systems. Now turning to our businesses, we are pleased that all product groups delivered double-digit year-over-year growth. Our IP business had an outstanding quarter growing over 40% year-over-year. AI performance is increasingly …
Cadence's integration of Hexagon's Design & Engineering business is on track, contributing to its system design & analysis revenue but also requiring investment.
… turning to our advanced packaging and PCB solutions. Allegro XAI was adopted by several customers driven by significant layout design time reduction. With our 3D IC technology and collaboration with TSMC's 3D Fabric Advanced Packaging Solutions, we are enabling customers to confidently design cutting-edge silicon for increasingly demanding AI workloads. In structural simulation, our beta CAE business had several competitive displacements. While the integration of recently acquired Hexagon's DNE business is progressing well with key deals closed with top customers. There is strong customer interest in our integrated full flow that combines our multi-physics products across the electrical, PFD, and structural domains to best address next generation system design needs, including in the emerging field of physical AI. In summary, Q2 was a great quarter for Cadence, and I'm delighted with the continued momentum of our business. With accelerating design activity, we continue to execute strongly, and our competitive position has never been better as we lead the transformation to agentic AI in chip and system design. With that, I will turn it over to John to provide more details on …
Cadence's hardware business (Palladium/Protium) remains supply-constrained by customer demand; systems are built as quickly as possible to meet backlog. — Persistent hardware tightness indicates that leading chip designers (including hyperscalers and semiconductor firms) are aggressively investing in verification capacity, a leading indicator of design activity.